Traditional EDA tools for physical design and verification have reached limits due to greater manufacturing process variability and the growing size and complexity of designs that take advantage of the latest nanometer scaling. With the advent of new process technologies, the handoff between integrated circuit (IC) layout and manufacturing has changed from a simple check to a multi-step process where the layout design must be enhanced to ensure efficient manufacturing. This presents a host of challenges related to manufacturing process effects, photolithography, data volumes, and achieving a cost-effective yield of finished chips from each wafer.
To meet these challenges with confidence, design teams turn to Mentor Graphic’s Olympus-SoC™ place and route system with Multi-Corner-Multi-Mode timing analysis and DFM-aware layout optimization for rapid closure of physical designs. The Olympus-SoC system works with the industry-leading integrated Calibre® design-to-silicon platform, which includes physical verification, full-chip, transistor-level parasitic extraction, model-based design for manufacturability (DFM) solutions, mask data preparation (MDP) and resolution enhancement technologies (RET), such as optical proximity correction and other computational lithography techniques. The Calibre product family efficiently and accurately manages every facet of the design-to-silicon transition.
The Mentor Graphics Tessent™ product suite is a comprehensive silicon test and yield analysis platform that addresses the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.
Tanner EDA by Mentor Graphics is an integrated, affordable and intuitive product suite for the design, layout and verification of analog/mixed signal (AMS) and Micro-Electro-Mechanical Systems (MEMS) ICs. Used by more than 25,000 designers around the world, Tanner tools support an end-to-end flow: top-down, mixed-signal design capture and simulation; synthesis with DFT support; physical design; place-and-route; and “sign-off ready” timing analysis to tape-out.
