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Figure 1: Different sizes of semiconductor wafers.
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Figure 2: Thin silicon wafer. Source: WaferWorld. [REF: Email from Ronnie Phelix, General Manager, Wafer World, Inc.]
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Figure 3: UnitySC provides thin wafer inspection systems.
Diane Hickey-Davis
Semiconductor wafers have gone on a diet. In certain segments of the industry, thin wafers are increasing in use in multiple devices. While the increase in silicon wafer diameter is well known, from 51 mm (2 inch) sizes in the early days to discussions of 450 mm today, and the “end” of Moore’s Law continues to end, or not, depending on physical limits or quantum gymnastics, another trend in semiconductor wafers is emerging – thin wafers.
What Does it Mean to be Thin?
A thin wafer is probably best defined by the rather boring description of “less than a standard thickness” of a wafer at a particular diameter. Various sizes of patterned silicon wafers are show in Image A, with a table of standard silicon wafer thickness in Table A (reference 1).
- 2-inch (51 mm). Thickness 275 µm.
- 3-inch (76 mm). Thickness 375 µm.
- 4-inch (100 mm). Thickness 525 µm.
- 5-inch (130 mm) or 125 mm (4.9 inch). Thickness 625 µm.
- 150 mm (5.9 inch, usually referred to as "6 inch"). Thickness 675 µm.
- 200 mm (7.9 inch, usually referred to as "8 inch"). Thickness 725 µm.
- 300 mm (11.8 inch, usually referred to as "12 inch"). Thickness 775 µm.
- 450 mm (17.7 inch). Thickness 925 µm (proposed)
What’s Driving the Diet?
Almost 20 years ago, EETimes reported on the use of thinner-than-standard wafers in it’s article "Schedule set for paper-thin chip technology". According to the article, the desire for thinner devices was being driven by the European use of smart cards. Just for fun, repeating the advances driving thin wafer technology as reported by the 1999 article:
"Probably the first application of this technology will be to stack flash memories in one SmartMedia card. A SmartMedia card has a 0.75-mm thickness, with a 0.5-mm opening to accommodate one flash-memory part. Using the thin semiconductor... Toshiba plans to ship samples of a 1-Gbit SmartMedia card that uses four stacked 256-Mbit flash devices."
In twenty years, we’ve gone way beyond stacking 256-Mbit flash devices, and the Internet of Things (IoT) will likely demand configurations barely conceivable two decades ago.
"The increase in use of thin wafers due to the rise of power semiconductors ICs for automotive applications," wrote Yann Guillou, the Global Marketing Manager of UnitySC that provides wafer surface and edge inspection solutions. A recent press release from the company suggests that this trend will only increase, "IHS Markit predicts USD $3 billion in global market growth for the power semiconductors used in cars and light passenger vehicles, over the next six years. Increasing electronic content is a key driver, particularly in hybrid and electric cars, due to consumer demand for constant connectivity. The automotive industry’s push to deliver autonomous, green vehicles in the next decade is also driving growth. These technologies rely on the latest power semiconductor devices, enabled by advanced wafer manufacturing processes like wafer thinning."
"New and old customers are asking for thinner wafers," said Sean Quinn, of Wafer World, Inc., which processes and supplies thin wafers to companies worldwide. He adds the specific thickness diamond requests include "75-100 microns in larger diameters like 150.0 mm with tighter thickness tolerance of ±5 microns."
When asked what's driving this need, Quinn states: "AI and MEMS for sensor based applications in environments with high stress or extreme accuracy."
What’s the Problem with Being Thin?
Many challenges come with creating and processing thin silicon wafers, and many more with non-silicon materials. In this article, we’ll highlight a few significant challenges being met in the industry:
- Processing
- Quality Assurance
- Dicing
Naturally, because we’re talking about semiconductors in the common era, scaling is never straightforward. For silicon wafers, the ability to double-side polish (DSP) while ensuring flatness is a challenge, as well as measuring the quality of the thin wafer, and then dicing a thin wafer adds another element.
How Flat is Thin? Polishing and Flatness
Thickness variation of wafers directly affects device yield. The desire (or need) to double-side polish (DSP) for specific devices presents additional challenges in keeping thickness variation to a minimum.
Ronnie Phelix, of Wafer World Inc., communicated that their company has focused on providing customers with thin, flat DSP silicon wafers with low total thickness variation, which directly impacts customer yield.
How Perfect is Thin? Measuring Quality in Thin Wafers
As usual when talking about wafer processes, yield and quality are intertwined. With the need for thinner wafers comes the need to measure the quality of thinner wafers.
“As the wafers used in power semiconductor manufacturing become thinner, controlling wafer quality through the backside thinning and metallization process steps becomes more critical to end-device performance and reliability,” said Gilles Fresquet, CEO, UnitySC. UnitySC is producing equipment to be able to detect defects after backgrinding, for wafers up to 300mm in diameter and down to 75 um in thickness (reference 3).
How to Dice Thin without sacrificing yield?
When it comes to dicing, scaling down in the thickness category is, again, not straightforward. According to a publication by ALSI, the dicing of wafers is facing a few major trends: thinner wafers, stronger die and non-silicon materials. For traditional thickness wafers, dicing was typically accomplished by physical means - using a saw or blade, various grits, and water as the die were physically separated.
With thin wafers, three options for dicing include not only physical (cutting) technology, but also laser techniques and plasma dicing.
Mechanical Dicing
In the 1999 article by EETimes, two companies were mentioned that introduced processing equipment to handle mechanical dicing of thinner wafers, which suffered greatly (from backside chipping) if diced like a traditional wafer. One of those companies was Disco, who today continues producing equipment for the processing of thinner and thinner wafers (reference 4).
According to the current Disco website, with the increased adoption of specialty electronics like IC cards, RFID tags and system-in-package for mobile devices, the market for thin semiconductor die 100 µm thick or less is growing. This high demand has in turn made the processing of thin wafers an essential competence for many device manufacturers (reference 4).
The challenge is that as a work piece grows thinner, dicing increases the likelihood of backside chipping. Disco is one of the companies providing equipment and processes that specifically address the challenges of dicing thin wafers (reference 4).
Laser Dicing
In a publication authored by Advanced Laser Separation International (ALSI), conventional physical (blade) dicing does not meet many of the separation requirements of today's processes, which not only use the thinner wafers, but also has the added complication of the use of Die Attach Film (DAF). The article notes that mechanical forces and vibrations can cause die crack and chip-outs and MEMS structures are extremely fragile and eliminate any technology that requires high-pressure water cleaning (reference 5).
The process of laser dicing wafers has developed to address many of the unique challenges. The use of lasers for dicing allows for many levels, or variables, to control and get the desired effectiveness, which are not available when using conventional mechanical dicing.
Plasma Dicing
A third option exists for dicing thinner wafers and smaller dies – plasma dicing. In an article describing the details of plasma dicing, Christopher Johnston of Plasma-Therm notes that plasma dicing reduces the challenges of mechanical dicing, like vibrations, as well as the challenges of thermal increases caused by laser dicing. He also adds that plasma dicing allows for additional benefits, such as unique geometries to reduce stress on chips (reference 6).
Conclusion
As the miniaturisation trend continues, and moves from the second dimension to the third dimension, multiple opportunities exists for companies and technologies that can solve some of the challenges with getting thin.
Dr. Diane Hickey-Davis is a principal of the Diamond Chameleon Group, a consultancy providing strategy and marketing services to scientists and engineers. She obtained her Ph.D. in Materials Science and Engineering at the University of Florida, studying MEMS fabrication and ion-implantation into materials such as single crystal diamond. She has worked professionally in business consulting, sales & marketing management, and new product development of MEMS devices. After working as an executive on a spin-out of Argonne National Lab in Chicago, she currently resides in the Tampa Bay area of Florida, USA. She is currently working with start-up companies in the micro fabrication and microscopy sectors.
References:
1) Table A. Source: Wikipedia: https://en.wikipedia.org/wiki/Wafer_(electronics)
2) Y. Hara, "Schedule set for paper-thin chip technology, " 1999, EETimes.com
3) UnitySC PR http://www.unity-sc.com/unitysc-receives-multiple-orders-wafer-thinning-inspection-systems/]
4) DISCO Inc. website http://www.discousa.com/eg/solution/library/dicing_thin.html
5) Enabling Technology in Thin Wafer Dicing.
Available from: https://www.researchgate.net/publication/266640892_Enabling_Technology_in_Thin_Wafer_Dicing [accessed Jun 29, 2017].
6) Johnston, Christopher. “Plasma dicing methods for thin wafers.” Chip Scale Review, May/June 2016 - http://www.plasma-therm.com/pdfs/CSR-Plasma-Dicing-Methods-Thin-Wafers.pdf
The author would also like to thank the following people for their input into this article: Yann Guillou, the Global Marketing Manager of UnitySC, Sean Quinn & WaferWorld BlogPost (https://www.waferworld.com/why-thinner-silicon-wafers-are-better-than-thicker/), Ronnie Phelix, General Manager, Wafer World Inc.