Functioning array of qubits with gaps between plunger (P) and barrier (B) gates of barely 6 nanometers, enabled by High NA EUV lithography. The image also shows the accumulation gates (A) and confinement (C).
The most advanced lithography system, crucial for future advanced memory and computer chips, will play a key role in scaling up quantum technology
This week, at ITF World, imec, a world-leading research and innovation hub in advanced semiconductor technologies, presents a world first: a quantum dot qubit device fabricated using High NA EUV lithography. This achievement marks a milestone toward the industrial scaling of more reliable qubits, the basic computational units of quantum computers. To the best of our knowledge, this is the first integrated hardware device created using High NA EUV lithography.
For specific, complex computational problems, such as developing new drugs or simulating physical processes, a quantum computer could perform exponentially better than classical computers. However, for a useful quantum computer, we need to scale to millions of connected qubits (the computational units of a quantum computer), with high reliability and precise control.
Of the various quantum platforms currently under investigation, silicon quantum dot spin qubits are considered a promising candidate for industrial scaling and are often referred to as ‘the industry qubits’. Their production process is largely compatible with the production of standard computer chips on silicon (CMOS), a research domain in which imec has built global authority over the past decades.
“We can leverage decades of semiconductor innovation and reuse the entire ecosystem of silicon scaling, moving quantum devices beyond lab experiments to large-scale, manufacturable systems. This is where silicon-based qubits have a clear advantage”, Sofie Beyne, project leader and quantum integration engineer at imec, explains.
Silicon quantum dot spin qubits confine an electron within a silicon nanostructure (the gate layer). The ‘spin state’ of the trapped electron is used to store quantum information. Gaps between the various gates must be minimized to limit environmental noise. Imec has succeeded in fabricating a functioning network of qubits with gaps of barely 6 nanometers. Thanks to the nanoscale of this hardware component, millions of quantum bits can theoretically be integrated onto a single chip.
“High NA EUV enables the precise patterning of silicon quantum dot qubits. As the coupling strength between neighboring quantum dots increases exponentially with the gap between them, we need to reliably pattern gaps of a few nanometers between the control electrodes of the quantum dots. This is a true engineering feat, thanks to our integration and patterning teams and ASML's outstanding high NA EUV technology”, says Kristiaan De Greve, imec fellow and program director Quantum Computing.
This demonstration builds on imec’s previous results with silicon quantum dot spin qubits, which already demonstrated that CMOS-compatible processes can lead to low charge noise and stable qubit operation. By adding High NA EUV lithography to the production process, the focus shifts from individual demonstration devices in the lab to 300mm fab-compatible, reproducible quantum bits.
While it’s obvious that High NA EUV lithography will be crucial for sub-2nm logic and high-density memory technologies that fuel the rapid growth of advanced AI and high-performance computing, it is now becoming clear that it will also play a pivotal role in hardware for future quantum computing.